Charge pump circuit and method

ABSTRACT

A charge pump circuit includes an output stage coupled to an output, a pumping stage between an input and the output stage, and a control circuit that outputs control signals. A pumping stage transistor includes S/D terminals coupled to input/output terminals, capacitive devices between signal terminals and either a transistor gate or a S/D terminal, and diode devices including either the anode/cathode or cathode/anode coupled to the respective gate and S/D terminal. An output stage transistor includes S/D terminals coupled to an input terminal and the output. One control signal includes a transition from first to second logic levels at a first time and another control signal includes a transition from the first to second logic levels at a second time, and a period between the transitions is sufficiently small to cause a change in a voltage at the pumping stage S/D terminal to be less than 100 millivolts.

PRIORITY CLAIM

The present application is a continuation of U.S. application Ser. No. 14/956,061, filed Dec. 1, 2015, which claims the priority of U.S. Provisional Application No. 62/087,365, filed Dec. 4, 2014, each of which is incorporated herein by reference in its entirety.

BACKGROUND

A charge pump circuit is a Direct Current (DC) to DC converter that generates a voltage having a voltage level higher (positive pump) than a voltage level of an input supply voltage or lower (negative pump) than a voltage level of a reference ground voltage. In some applications, a charge pump circuit includes capacitors as energy storage elements and transistors as storage transfer elements. In some applications, the transistors are turned on or off responsive to various control signals, and the control signals are bounded by the voltage levels of the input supply voltage and the reference ground voltage. Also, various drain/source terminals of the transistors have up/down shifted voltages by the operations of charging and level-shifting the voltage levels at the capacitors of the charge pump circuit. In some applications, the various up/down shifted voltages have voltage levels beyond the voltage range between the input supply voltage and the reference ground voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a functional block diagram of a charge pump circuit, in accordance with some embodiments.

FIG. 2 is a circuit schematic diagram of a pumping stage circuit usable in the charge pump circuit in FIG. 1 , in accordance with some embodiments.

FIG. 3 is a circuit schematic diagram of an output stage circuit usable in the charge pump circuit in FIG. 1 , in accordance with some embodiments.

FIG. 4 is a circuit schematic diagram of a control circuit usable in the charge pump circuit in FIG. 1 , in accordance with some embodiments.

FIGS. 5A and 5B are circuit schematic diagrams of two example diode devices usable as the diode devices in the pumping stage circuit in FIG. 2 or in the output stage circuit in FIG. 3 , in accordance with some embodiments.

FIG. 6 is a timing diagram of voltage levels at various nodes of the charge pump circuit in FIG. 1 , which is further illustrated in conjunction with FIGS. 2-4 , in accordance with some embodiments.

FIG. 7 is a flow chart of a method of operating a pumping stage circuit in FIG. 2 , in accordance with some embodiments.

FIG. 8 is a circuit schematic diagram of a signal generation circuit usable in the control circuit of FIG. 4 , in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a pumping stage circuit or an output stage circuit of a charge pump circuit includes a transistor, a capacitive device coupled with a gate terminal of the transistor, and two diode devices between the gate terminal and a source/drain (S/D) terminal of the transistor. The two diode devices are coupled in an inverse-parallel manner. Through a discharge path provided by one of the two diode devices and the DC separation between the gate terminal of the transistor and a driving signal, the voltage difference between the gate terminal and the S/D terminal is kept at about a forward voltage drop of the one of the two diode devices.

FIG. 1 is a functional block diagram of a charge pump circuit 100, in accordance with some embodiments. Charge pump circuit 100 includes an input node 102, an output node 104, a reference voltage terminal 106, N pumping stage circuits 110[1], 110[2], and 110[N], an output stage circuit 120, and a control circuit 130. N is a positive integer equal to or greater than one. Three pumping stage circuits 110[1], 110[2], and 110[N] (i.e., N=3) are depicted in FIG. 1 as a non-limiting example. Pumping stage circuits 110[1], 110[2], and 110[N] and output stage circuit 120 are coupled between input node 102 and output node 104. Control circuit 130 is coupled with output node 104 and reference voltage terminal 106, and is configured to generate a plurality of control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] for controlling the operation of pumping stage circuits 110[1], 110[2], and 110[N] and output stage circuit 120.

Each pumping stage circuit of pumping stage circuits 110[1], 110[2], and 110[N] includes an input terminal IN, an output terminal OUT, and control signal terminals SW and CP. Output stage circuit 120 includes an input terminal IN, an output terminal OUT, and a control signal terminal SW. The input terminal IN of the first pumping stage circuit 110[1] is coupled with the input node 102. The output terminal OUT of a n-th pumping stage circuit 110[n] is coupled with the input terminal IN of a (n+1)-th pumping stage circuit 110[n+1], where n is a positive integer and 1≤n≤(N−1). The output terminal OUT of the N-th pumping stage circuit 110[N] is coupled with the input terminal IN of the output stage circuit 120. The output terminal OUT of the output stage circuit 120 is coupled with the output node 104.

In some embodiments, pumping stage circuits 110[1], 110[2], and 110[N] are configured to convert a voltage at input node 102 having a voltage level V_(IN) to a predetermined voltage level V_(OUT) at output node 104. During a steady state operation of charge pump circuit 100 and with transient overshoots or undershoots ignored, the voltage level at output terminal OUT of pumping stage circuit 110[1] switches between V_(IN) and V₁; the voltage level at output terminal OUT of pumping stage circuit 110[2] switches between V₁ and V₂; the voltage level at input terminal IN of pumping stage circuit 110[N] switches between V_(N−2) and V_(N−1); and the voltage level at output terminal OUT of pumping stage circuit 110[N] switches between V_(N−1) and V_(OUT). In some embodiments, the voltage level at output terminal OUT of pumping stage circuit 110[n] switches between V_(n−1) and V_(n) according to the following equations:

ΔV=V _(OUT) −V _(N)   (1)

V ₀ =V _(N)   (2)

V _(N) =V _(OUT); and   (3)

V _(n) =V _(N) +n*(ΔV/N), n is a positive integer and 1≤n≤(N−1)   (4)

In some embodiments, voltage level V_(OUT) is greater than voltage level V_(IN), charge pump circuit 100 functions as a positive pump, and ΔV thus has a positive value. In some embodiments, voltage level V_(OUT) is less than voltage level V_(IN), charge pump circuit 100 functions as a negative pump, and ΔV thus has a negative value.

Furthermore, control signal terminal SW of pumping stage circuit 110[1] is configured to receive control signal SW[1]; and control signal terminal CP of pumping stage circuit 110[1] is configured to receive control signal CP[1]. Control signal terminal SW of pumping stage circuit 110[2] is configured to receive control signal SW[2]; and control signal terminal CP of pumping stage circuit 110[2] is configured to receive control signal CP[2]. Control signal terminal SW of pumping stage circuit 110[N] is configured to receive control signal SW[N]; and control signal terminal CP of pumping stage circuit 110[N] is configured to receive control signal CP[N]. Control signal terminal SW of output stage circuit 120 is configured to receive control signal SWF. Example implementations and operation of pumping stage circuits 110[1], 110[2], and 110[N] and output stage circuit 120 in response to various control signals are further described in detail in conjunction with FIGS. 2 and 6 .

Control circuit 130 is coupled with output node 104 and reference voltage terminal 106 and is configured to generate the plurality of control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] based on the voltage level V_(OUT) at output node 104 and a reference voltage level V_(REF) at reference voltage terminal 106. In some embodiments, a signal SW[n] and a corresponding signal CP[n] have the same waveform. In some embodiments, a signal SW[n] has a pulse width of the voltage level (corresponding to the logic high value) different than that of a corresponding signal CP[n].

In some embodiments, all odd-numbered signals SW[n] have the same first waveform, and all even-numbered signals SW[n] have the same second waveform. In some embodiments, the first waveform and the second waveform are not at a voltage level corresponding to a logic high value concurrently, and odd-numbered signals SW[n] and even-numbered signals SW[n] are thus referred to as non-overlapping signals. In some embodiments, all odd-numbered signals CP[n] have the same third waveform, and all even-numbered signals CP[n] have the same fourth waveform. In some embodiments, the third waveform and the fourth waveform are not concurrently at the voltage level corresponding to a logic high value, and odd-numbered signals CP[n] and even-numbered signals CP[n] are thus referred to as non-overlapping signals.

An example implementation and operation of control circuit 130 are further described in detail in conjunction with FIG. 4 .

FIG. 2 is a circuit schematic diagram of a pumping stage circuit 200 usable in charge pump circuit 100 in FIG. 1 , in accordance with some embodiments. In some embodiments, pumping stage circuit 200 is usable as any one or all of pumping stage circuits 110[1], 110[2], and 110[N].

Pumping stage circuit 200 includes an input terminal IN, an output terminal OUT, and control signal terminals SW and CP variously corresponding to the terminals IN, OUT, SW, and CP of pumping stage circuits 110[1], 110[2], or 110[N] in FIG. 1 . For illustration, input terminal IN has a voltage V_(s), and output terminal OUT has a voltage V_(D). Control signal terminal SW is configured to receive a control signal S₁, which corresponds to control signal SW[1], SW[2], or SW[N]. Control signal terminal CP is configured to receive a control signal S₂, which corresponds to control signal CP[1], CP[2], or CP[N].

Pumping stage circuit 200 includes a transistor 210, a first capacitive device 222, a second capacitive device 224, a first diode device 232, a second diode device 234, a first driver 242, and a second driver 244.

Transistor 210 is an N-type transistor and functions as a switching device. In some embodiments, transistor 210 is implemented by a P-type transistor or other suitable switching devices. Transistor 210 includes a gate terminal 212, a first S/D terminal 214, and a second S/D terminal 216. First S/D terminal 214 is coupled with input terminal IN. Second S/D terminal 216 is coupled with output terminal OUT. Gate terminal 212 has a voltage V_(G).

First capacitive device 222 has a first end coupled with the gate terminal 212 of transistor 210 and a second end configured to receive a driving signal S₃. Second capacitive device 224 has a first end coupled with the output terminal OUT and a second end configured to receive a driving signal S₄. First diode device 232 has a cathode coupled with second S/D terminal 216 of transistor 210 and an anode coupled with gate terminal 212 of transistor 210. Second diode device 234 has a cathode coupled with gate terminal 212 of transistor 210 and an anode coupled with second S/D terminal 216 of transistor 210.

First driver 242 is configured to generate the driving signal S₃ based on the control signal S₁. Second driver 244 is configured to generate the driving signal S₄ based on the control signal S₂. First driver 242 is an inverter having an input terminal coupled with control signal terminal SW and an output terminal coupled with the second end of capacitive device 222. Second driver 244 is an inverter having an input terminal coupled with control signal terminal CP and an output terminal coupled with the second end of capacitive device 224. In some embodiments, first driver 242 and second driver 244 are implemented by one or a combination of an inverter, a buffer, a level shifter, or other suitable devices. In some embodiments, each signal of signal S₁, S₂, S₃, and S₄ switches between a first voltage level corresponding to a logic high value (hereinafter the “first logic high level”) and a reference ground voltage level corresponding to a logic low value (hereinafter the “logic low level”). In some embodiments, each signal of signals S₃ and S₄ switches between the first logic high level and the logic low level, and each signal of signals S₁ and S₂ switches between a second voltage level corresponding to the logic high value (hereinafter the “second logic high level”) and the logic low level. In some embodiments, the second logic high level is greater than the first logic high level.

A diode device has a forward voltage drop between an anode and a cathode thereof when the diode device is forward biased and conductive. In some embodiments, first diode device 232 has a forward voltage drop V_(FB1), second diode device 234 has a forward voltage drop V_(FB2), and forward voltage drop V_(FB1) is greater than forward voltage drop V_(FB2). Also, transistor 210 has a threshold voltage V_(TH) between gate terminal 212 and S/D terminal 216. In some embodiments, forward voltage drop V_(FB1) is greater than threshold voltage V_(TH) of transistor 210.

In some embodiments, diode device 232 is configured to provide a discharge path between gate terminal 212 and S/D terminal 216 in order to reduce a voltage difference between voltage V_(G) and voltage V_(D) to be no greater than forward voltage drop V_(FB1) of diode device 232 when diode device 232 is forward biased and conductive. In some embodiments, diode device 234 is configured to provide a discharge path between gate terminal 212 and S/D terminal 216 in order to limit a voltage difference between voltage V_(G) and voltage V_(D) to be no greater than forward voltage drop V_(FB2) of diode device 234 when diode device 234 is forward biased and conductive. In some embodiments, diode devices 232 and 234 also provide conductive paths to reduce the peak voltage levels of voltage V_(G) and voltage V_(D) when these voltages are being switched in response to the transitions of signals S₃ and S₄ and by the operation of capacitive devices 222 and 224.

In operation, diode devices 232 and 234 thereby act to guarantee that the DC value on capacitor 222 is always in the correct range in order to turn on and off transistor 210.

In some embodiments, diode device 232 includes a series of one or more diodes and forward voltage drop V_(FB1) of diode device 232 is the sum of the voltage drops of each diode of the diode series. In some embodiments, diode device 234 includes a series of one or more diodes and forward voltage drop V_(FB2) of diode device 234 is the sum of the voltage drops of each diode of the diode series.

In operation, capacitive device 222 level-shifts driving signal S₃ such that the need to generate control signals having a large voltage swing is avoided. This feature simplifies circuit design and makes it possible to implement a charge pump without the costs associated with a high voltage capability. Detailed operation of various components of pumping stage circuit 200 is illustrated in conjunction with FIG. 6 .

FIG. 3 is a circuit schematic diagram of an output stage circuit 300 usable in charge pump circuit 100 in FIG. 1 , in accordance with some embodiments. Components in FIG. 3 that are the same or similar to those in FIG. 2 are given the same reference labels, and detailed description thereof is thus omitted.

Compared with pumping stage circuit 200, output stage circuit 300 does not have control signal terminal CP and driver 244. Capacitive device 224 is coupled between output terminal and a supply reference terminal 310. In some embodiments, supply reference terminal 310 has a voltage level corresponding to a reference ground voltage level or the zero volt level. In some embodiments, supply reference terminal 310 has a voltage level the same as the logic low level.

In operation, output stage circuit 300 stores and holds at capacitive device 224 the charges from a previous pumping stage circuit and outputs a voltage at output terminal OUT having a predetermined pumped voltage level. The capacitance value of the capacitive device 224 in the output stage circuit 300 is set to be sufficiently large to substantially hold the predetermined pumped voltage level while allowing a predetermined current to be drawn by an external circuit.

FIG. 4 is a circuit schematic diagram of a control circuit 400 usable in charge pump circuit 100 in FIG. 1 , in accordance with some embodiments.

Control circuit 400 includes a feedback voltage terminal 402, a reference voltage terminal 404, a supply voltage terminal 408, resistive devices 412 and 414, a comparator 420, a signal generation circuit 430, and a plurality of control lines 440. In some embodiments, control circuit 400 includes a clock terminal 406.

Feedback voltage terminal 402 is coupled with output node 104 of charge pump circuit 100. Reference voltage terminal 404 is configured to receive a reference voltage having the reference voltage level V_(REF). Supply voltage terminal 408 is configured to carry a voltage having a supply voltage level. In some embodiments, the supply voltage level is the same as the first logic high level or the second logic high level. Resistive devices 412 and 414 are coupled in series between supply voltage terminal 408 and feedback voltage terminal 402. Resistive devices 412 and 414 are configured as a voltage divider to convert the voltage at output node 104 to a feedback voltage having a voltage level V_(FB) comparable to the reference voltage level V_(REF).

Comparator 420 includes a first input terminal 422, a second input terminal 424, and an output terminal 426. First input terminal 422 is configured to receive the reference voltage (having the reference voltage level V_(REF)). Second input terminal 424 is configured to receive the feedback voltage (having the feedback voltage level V_(FB)). Comparator 420 compares the values of reference voltage level V_(REF) and feedback voltage level V_(FB) and generates a comparison result at output terminal 426.

Signal generation circuit 430 is coupled with the output terminal 426 of comparator 420 and, if present, clock terminal 406. Signal generation circuit 430 is also coupled with pumping stage circuits 110[1], 110[2], and 110[N] and output stage circuit 120 through the plurality of control lines 440. Signal generation circuit 430 is configured to receive the comparison result at output terminal 426 of comparator 420 and a clock signal CLK from clock terminal 406, and generate control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] on the plurality of control lines 440. In some embodiments, signal generation circuit 430 is further configured to receive a clock signal CLK from clock terminal 406.

Control circuit 400 is a non-limiting example. Other types of control circuits usable to generate control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] to control charge pump circuit 100 based on the pulse width, frequencies, or amplitude information thereof are within the scope of various embodiments of the present disclosure.

FIG. 8 is a circuit schematic diagram of an example signal generation circuit 800 usable as a signal generation circuit 430 in the control circuit in FIG. 4 , in accordance with some embodiments.

Signal generation circuit 800 includes a D-flip-flop (DFF) 802, an AND gate 804, and a two-phase, non-overlapping clock generator 808. DFF 802 includes a clock input terminal 806 and a comparator input terminal 826. Two-phase, non-overlapping clock generator 808 includes a first output terminal 810 and a second output terminal 812.

DFF 802 is configured to receive clock signal CLK at clock input terminal 806 and to receive a comparator output, e.g. the comparison result at output terminal 426, at logic input terminal 826. DFF 802 samples the comparator output based on clock signal CLK and outputs a sampled comparator output.

AND gate 804 is configured to receive the sampled comparator output from DFF 802 and clock signal CLK, and provide a gated output to two-phase, non-overlapping clock generator 808. In response to a logic high level of the sampled comparator output, AND gate 804 is configured to output a gated clock signal. In response to a logic low level of the sampled comparator output, AND gate 804 is configured to output a logic low level.

Two-phase, non-overlapping clock generator 808 is configured to receive the gated clock signal from AND gate 804, and in response, create a first pulse signal A at first output terminal 810 and a second pulse signal B at second output terminal 812. In some embodiments, first pulse signal A and second pulse signal B are used as charge pump control signals SW[i] and CP[i]. In some embodiments, first output terminal 810 and second output terminal 812 are coupled with the plurality of control lines 440.

In some embodiments, first pulse signal A is used as charge pump control signal SW[i] for even values of i and second pulse signal B is used as charge pump control signal SW[i] for odd values of i.

In some embodiments, first pulse signal A is used as charge pump control signal CP[i] for odd values of i and second pulse signal B is used as charge pump control signal CP[i] for even values of i.

In operation, signal generation circuit 800 responds to the comparator output by generating first pulse signal A and second pulse signal B when feedback voltage level V_(FB) is above reference voltage level V_(REF), and by not generating first pulse signal A and second pulse signal B when feedback voltage level V_(FB) is below reference voltage level V_(REF).

Signal generation circuit 800 is a non-limiting example. Other types of signal generation circuits usable to generate control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] to control charge pump circuit 100, including signal generation circuits without a clock signal input, are within the scope of various embodiments of the present disclosure.

FIG. 5A is a circuit schematic diagram of an example diode device 500A usable as a diode device 232 or 234 in pumping stage circuit 200 in FIG. 2 or in output stage circuit 300 in FIG. 3 , in accordance with some embodiments.

Diode device 500A includes an anode terminal 502, a cathode terminal 504, and J diode-connected P-type transistors 510[1] to 510[J] between anode terminal 502 and cathode terminal 504. J is a positive integer greater than zero. P-type transistors 510[1] to 510[J] are coupled in series when J is greater than one. To implement diode device 242 and diode device 244 using a configuration based on diode device 500A, diode device 242 is configured to have X (J=X) diode-connected transistors 510[1] to 510[X], and diode device 244 is configured to have Y (J=Y) diode-connected transistors 510[1] to 510[Y], where X and Y are positive integers. In some embodiments, diode device 242 has a forward voltage drop V_(FB1) greater than a forward voltage drop V_(FB2) of diode device 244. Therefore, Y is set to be less than X.

FIG. 5B is a circuit schematic diagram of another example diode device 500B usable as a diode device 232 or 234 in pumping stage circuit 200 in FIG. 2 or in output stage circuit 300 in FIG. 3 , in accordance with some embodiments. Components in FIG. 5B that are the same or similar to those in FIG. 5A are given the same reference labels, and detailed description thereof is thus omitted.

Diode device 500B includes K diode-connected N-type transistors 520[1] to 520[K] between anode terminal 502 and cathode terminal 504. K is a positive integer greater than zero. N-type transistors 520[1] to 520[K] are coupled in series when K is greater than one. To implement diode device 232 and diode device 234 using a configuration based on diode device 500B, diode device 232 is configured to have X (K=X) diode-connected transistors 520[1] to 520[X], and diode device 234 is configured to have Y (K=Y) diode-connected transistors 520[1] to 520[Y], where X and Y are positive integers. In some embodiments, diode device 232 has a forward voltage drop V_(FB1) greater than a forward voltage drop V_(FB2) of diode device 234. Therefore, Y is set to be less than X.

In some embodiments, one of diode device 232 or diode device 234 is implemented based on the configuration of diode device 500A, and the other one of diode device 232 or diode device 234 is implemented based on the configuration of diode device 500B. In some embodiments, diode device 232 or diode device 234 is implemented by other types of diode devices different from diode device 500A and diode device 500B.

FIG. 6 is a timing diagram of voltage levels at various nodes of charge pump circuit 100 in FIG. 1 , which is further illustrated in conjunction with FIGS. 2-4 , in accordance with some embodiments.

In the example depicted in FIG. 6 , the number of pumping stage circuits (i.e., the number N in FIG. 1 ) is set to be two, and charge pump circuit is configured to be a negative pump. The voltage level V_(IN) is set to be 0 V, and the voltage level V_(OUT) is set to be −2.2 V. The charge pump circuit as illustrated in conjunction with FIGS. 1-4 is also usable as a positive pump. Different configurations and settings of the charge pump circuit 100 are within various embodiments of the present disclosure.

Waveform 602 corresponds to the voltage level of signal S₁ of first pumping stage circuit 110[1]. Waveform 604 corresponds to the voltage level of signal S₂ of first pumping stage circuit 110[1]. Waveform 612 corresponds to the voltage level of voltage V_(D) of first pumping stage circuit 110[1]. Waveform 614 corresponds to the voltage level of voltage V_(G) of first pumping stage circuit 110[1]. Waveform 622 corresponds to the voltage level of voltage V_(D) of second pumping stage circuit 110[2]. Waveform 632 corresponds to the voltage level of voltage V_(D) of output stage circuit 120.

The following illustration, if not otherwise specified, is primarily based on the operation of first pumping stage circuit 110[1] using the reference labels from pumping stage circuit 200 in FIG. 2 . The operations of transistors 210 and capacitive device 222 of second pumping stage circuit 110[2] and output stage circuit 120 are similar to the operations of transistor 210 and capacitive device 222 of first pumping stage circuit 110[1]. The operation of capacitive device 224 of second pumping stage circuit 110[2] is similar to the operation of capacitive device 224 of first pumping stage circuit 110[1]. Detailed description thereof is thus omitted.

In this embodiment, each signal of signals S₁, S₂, S₃, and S₄ has a logic high level of 1.8 volts (V) and a logic low level of 0.0 V. In some embodiments, each signal of signals S₁ and S₃ has a logic high level different from that of signal S₂ and S₄. In some embodiments, each signal of signals S₁ and S₃ has a logic high level of 2.5 V, and each signal of signals S₂ and S₄ has a logic high level of 1.8 V.

Prior to time T₁ during a steady state operation of charge pump circuit 100, signal S₁ (waveform 602) and signal S₂ (waveform 604) of first pumping stage circuit 110[1] are at the low logic level. Signal S₃ (not shown) and signal S₄ (not shown) of first pumping stage circuit 110[1] are thus at the signal high level. Voltage V_(D) of first pumping stage circuit 110[1] is at an input voltage level from a power source or a previous pumping stage circuit, such as 0.0 volt for first pumping stage circuit 110[1] in this example. Also, voltage V_(G) of first pumping stage circuit 110[1] is at a voltage level that equals the input voltage level plus the forward voltage drop V_(FB1) of diode device 232, such as V_(FB1) in this example. Because forward voltage drop V_(FB1) is set to be greater than threshold voltage V_(TH) of transistor 210, transistor 210 is turned on to pass the input voltage level (e.g., 0.0 V in this example) to voltage V_(D).

At time T₁, signal S₁ (waveform 602) transitions from the low logic level to the high logic level. Signal S₂ (waveform 604) remains at the low logic level. Signal S₃ (not shown) thus transitions from the high logic level to the low logic level while signal S₄ (not shown) remains at the signal high level. Through the operation of capacitive device 222 of first pumping stage circuit 110[1], at time T₁, voltage V_(G) (waveform 614) of first pumping stage circuit 110[1] is pushed down by about 1.8 V. Meanwhile, diode device 234 of first pumping stage circuit 110[1] is also providing a discharge path to pull voltage V_(G) (waveform 614) and voltage V_(D) (waveform 612) toward each other. As a result of these contradictory pulling forces, at time T₁, voltage V_(G) (waveform 614) transitions from voltage level V_(FB1) to a voltage level that is a few hundred millivolts (mV) higher than a voltage level of voltage level V_(FB1) minus 1.8 V. The voltage differences between the gate terminal of transistor 210 and S/D terminals of transistor 210 are insufficient to turn on transistor 210. Voltage V_(D) (waveform 614) remains at 0.0 V. Transistor 210 is thus turned off.

After time T₁ but before time T₂, voltage V_(G) (waveform 614) and voltage V_(D) (waveform 612) are pulled toward each other through diode device 234. Transistor 210 remains turned off. In some embodiments, the time period between time T₁ and time T₂ is set to be insufficient to pull voltage V_(G) to be sufficiently large to turn on transistor 210 at time T₂. In some embodiments, the time period between time T₁ and time T₂ is sufficiently small that the voltage change of voltage V_(G) (waveform 614) or the voltage change of voltage V_(D) (waveform 612) is less than 100 mV.

At time T₂, signal S₂ (waveform 604) transitions from the low logic level to the high logic level. Signal S₁ (waveform 602) remains at the high logic level. Signal S₄ (not shown) thus transitions from the high logic level to the low logic level while signal S₃ (not shown) remains at the signal low level. Through the operation of capacitive device 224, at time T₂, voltage V_(D) (waveform 612) is being pushed down by about 1.8 V. Meanwhile, through the charge sharing between capacitive device 224 and another capacitive device of the next pumping stage circuit (e.g., capacitive device 224 of second pumping stage circuit 110[2]) or a corresponding output stage circuit 120 (e.g., capacitive device 224 of output stage circuit 120), voltage V_(D) is also being pulled toward a steady state output voltage level of this pumping stage, such as −1.1 V in this example. In some embodiments, the charge sharing is also controlled by adjusting the frequencies of control signals SW[1], SW[2], SW[N], SWF, CP[1], CP[2], and CP[N] and/or by adjusting the voltage level of signal S₄. Voltage V_(G) (waveform 314) is pulled down slightly at time T₂ when diode device 234 goes from conductive to reverse-biased. As a result, at time T₂, voltage V_(D) (waveform 612) transitions from 0.0 V to a voltage level that is a few hundred mV higher than a voltage level of −1.8 V. Transistor 210 remains turned off.

After time T₂ but before time T₃, voltage V_(G) (waveform 614) remains at about the same voltage level after diode devices 232 and 234 reach their charge balance states after being turned off. Voltage V_(D) (waveform 612) is pulled toward and then remains at the steady state output voltage level (e.g., −1.1 V in this example). In this example, the voltage level of V_(G) is greater than the voltage level of V_(D), but the voltage difference therebetween is insufficient to turn on transistor 210. Transistor 210 remains turned off.

At time T₃, signal S₂ (waveform 604) transitions from the high logic level to the low logic level. Signal S₁ (waveform 602) remains at the high logic level. Signal S₄ (not shown) thus transitions from the low logic level to the high logic level while signal S₃ (not shown) remains at the signal low level. Through the operation of capacitive device 224, at time T₃, voltage V_(D) (waveform 612) is being pulled up by about 1.8 V. Meanwhile, diode device 234 is also providing a discharge path to pull voltage V_(G) (waveform 614) and voltage V_(D) (waveform 612) toward each other. As a result, at time T₃, voltage V_(D) (waveform 612) transitions from the steady state output voltage level (e.g., −1.1 V in this example) to a voltage level that is a few hundred mV lower than a voltage level of 0.7 V (i.e, −1.1 V plus 1.8 V). The voltage differences between the gate terminal of transistor 210 and S/D terminals of transistor 210 are insufficient to turn on transistor 210. Transistor 210 remains turned off.

After time T₃ but before time T₄, voltage V_(G) (waveform 614) and voltage V_(D) (waveform 612) are pulled toward each other through diode device 234. Transistor 210 remains turned off. In some embodiments, the time period between time T₃ and time T₄ is sufficiently small that the voltage change of voltage V_(G) (waveform 314) or the voltage change of voltage V_(D) (waveform 612) is less than 100 mV.

At time T₄, signal S₁ (waveform 602) transitions from the high logic level to the low logic level. Signal S₂ (waveform 604) remains at the low logic level. Signal S₃ (not shown) thus transitions from the low logic level to the high logic level while signal S₄ (not shown) remains at the signal high level. Through the operation of capacitive device 222, at time T₄, voltage V_(G) (waveform 614) is being pulled up by about 1.8 V. Meanwhile, diode device 232 is also providing a discharge path to pull voltage V_(G) (waveform 614) toward voltage V_(D). As a result, at time T₄, voltage V_(G) (waveform 614) transitions to a voltage level that is a few hundred mV higher than voltage level V_(FB1). The voltage difference between the gate terminal of transistor 210 and S/D terminal 216 is sufficient to turn on transistor 210.

After time T₄ but before time T₅, voltage V_(D) (waveform 612) is pulled toward and then remains at the steady state input voltage level (e.g., 0 V in this example), and voltage V_(G) (waveform 614) is pulled toward and then remains at about forward voltage drop V_(FB1) of diode device 232 plus the steady state input voltage level. Transistor 210 remains turned on.

At time T₅, the next operation cycle of pumping stage circuit 200 begins. Time T₅ corresponds to time T₁ of the next operation cycle.

Second pumping stage circuit 110[2] is operated in a manner similar to first pumping stage circuit 110[1], except the corresponding control signals thereof are non-overlapping signals to the counterpart signals of first pumping stage circuit 110[1]. As a result, voltage V_(D) of pumping stage circuit 110[2] (waveform 622) is at −1.1V during time T₁ to time T₄ and is pumped to −2.2 V during time T₄ to time T₅. Transistor 210 of output stage circuit 120 is operated in a manner similar to transistor 210 of first input stage 110[1]. Capacitive device 224 of output stage circuit 120 is configured to hold the voltage level of voltage V_(D) at −2.2 V when transistor 210 of output stage circuit 120 is turned off during time T₁ to time T₄. Capacitive device 224 of output stage circuit 120 is also configured to receive the charges from the capacitive device 224 of second pumping stage circuit 110[2] when transistor 210 of output stage circuit 120 is turned on during time T₄ to time T₅. As a result, voltage V_(D) of output stage circuit 120 remains at −2.2 V.

As depicted in FIG. 6 and FIG. 2 , through the discharge path provided by diode device 232 and the DC separation between gate terminal 212 of transistor 210 and the output terminal of driver 242 (i.e., signal S₃), the voltage difference between gate terminal 212 and S/D terminal 216 and the voltage difference between gate terminal 212 and S/D terminal 214 when transistor 210 is turned on is kept at about forward voltage drop V_(FB1) of diode device 232. In some embodiments, forward voltage drop V_(FB1) of diode device 232 is set to be less than the logic high level, such as 1.8 V in this example. For a pump stage circuit at a later stage of the charge pump circuit 100 or the output stage circuit 120, regardless the corresponding input voltage level or the pumped voltage level, a transistor corresponding to transistor 210 thus has a gate terminal to S/D terminal voltage adjusted by forward voltage drop V_(FB1) of diode device 232, which is less than the logic high level when the transistor 210 is turned on.

FIG. 7 is a flow chart of a method 700 of operating a pumping stage circuit in FIG. 2 , in accordance with some embodiments. FIG. 7 is illustrated in conjunction with the example depicted in FIG. 2 . It is understood that additional operations may be performed before, during, and/or after the method 700 depicted in FIG. 7 , and that some other processes may only be briefly described herein.

Method 700 begins with operation 710, where a voltage level at a first end of a capacitive device, such as signal S₃ between driver 242 and capacitive device 222, is caused to transition from a first voltage level to a second voltage level responsive to a first logic value of a control signal. In some embodiments, the first voltage level corresponds to a logic low level, the second voltage level corresponds to a logic high level, the control signal corresponds to signal S₁, and the first logic value corresponds to a logic low value.

Method 700 proceeds to operation 720, where a voltage level at a second end of capacitive device 222, such as voltage V_(G), is caused to transition to a third voltage level responsive to the second voltage level at the first end of the capacitive device. The second end of capacitive device 222 is electrically coupled with a gate terminal 212 of a transistor 210.

In some embodiments, operations 710 and 720 correspond to the signal transitions at time T₄ in the timing diagram in FIG. 6 .

Method 700 proceeds to operation 730, where a first voltage difference between gate terminal 212 and a source/drain (S/D) terminal 216 of transistor 210 is adjusted by a first diode device, such as diode device 232, when transistor 210 is turned on and first diode device 232 is forward biased and conductive. First diode device 232 has an anode coupled with gate terminal 212 of transistor 210 and a cathode coupled with S/D terminal 216 of transistor 210. In some embodiments, operation 730 corresponds to the signal transitions from time T₄ to time T₅ in the timing diagram in FIG. 6 .

Method 700 proceeds to operation 740, where a voltage level (e.g., signal S₃) at the first end of capacitive device 222 is caused to transition from the second voltage level to the first voltage level responsive to a second logic value of a control signal. In some embodiments, the second logic value corresponds to a logic high value. As a result, voltage V_(G) is caused to transition to a fourth voltage level that is insufficient to turn on transistor 210. In some embodiments, operation 740 corresponds to the signal transitions at time T₁ in the timing diagram in FIG. 6 .

Method 700 proceeds to operation 750, where a second voltage difference between S/D terminal 216 of the transistor 210 and gate terminal 212 of transistor 201 is adjusted by a second diode device, such as diode device 234, when the transistor 210 is turned on and the second diode device 234 is forward biased and conductive. Second diode device 234 has an anode coupled with the S/D terminal 216 of the transistor 210 and a cathode coupled with the gate terminal 212 of the transistor 210. In some embodiments, operation 750 corresponds to the signal transitions from time T₁ to time T₂ and/or from time T₃ to time T₄ in the timing diagram in FIG. 6 .

In some embodiments, first diode device 232 has a forward voltage drop V_(FB1), second diode device 234 has a forward voltage drop V_(FB2), and forward voltage drop V_(FB1) is greater than forward voltage drop V_(FB2). Also, transistor 210 has a threshold voltage V_(TH) between gate terminal 212 and S/D terminal 216. In some embodiments, forward voltage drop V_(FB1) is greater than threshold voltage V_(TH) of transistor 210.

In some embodiments, operations 710-750 are applicable to a method of operating an output stage circuit 300 in FIG. 3 .

Method 700 proceeds to operation 760, where a voltage level at S/D terminal 216 of transistor 210 is pumped to a predetermined pumped voltage level in response to another control signal, such as control signal S₂. In some embodiments, operation 760 corresponds to the signal transitions from time T₂ to time T₃ in the timing diagram in FIG. 6 .

In some embodiments, a charge pump circuit includes input and output nodes, an output stage circuit coupled to the output node, a pumping stage circuit coupled between the input node and the output stage circuit, and a control circuit configured to output first and second control signals to respective first and second control signal terminals of the pumping stage circuit. The pumping stage circuit includes a first input terminal, an output terminal, a first transistor including a first S/D terminal coupled to the first input terminal, a second S/D terminal coupled to the output terminal, and a first gate terminal, a first capacitive device coupled between the first control signal terminal and the first gate terminal, a second capacitive device coupled between the second control signal terminal and the second S/D terminal, a first diode device including a first anode coupled to the first gate terminal and a first cathode coupled to the second S/D terminal, and a second diode device including a second cathode coupled to the first gate terminal and a second anode coupled to the second S/D terminal, the output stage circuit includes a second input terminal and a second transistor including a third S/D terminal coupled to the second input terminal and a fourth S/D terminal coupled to the output node, the control circuit is configured to generate the first control signal including a first transition from a first logic level to a second logic level at a first time and the second control signal including a second transition from the first logic level to the second logic level at a second time, and a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the second S/D terminal of the first transistor from the first time to the second time to be less than 100 millivolts. In some embodiments, the control circuit is configured to generate the second control signal including a third transition from the second logic level to the first logic level at a third time and the first control signal including a fourth transition from the second logic level to the first logic level at a fourth time, and another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the second S/D terminal of the first transistor from the third time to the fourth time to be less than 100 millivolts. In some embodiments, a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device. In some embodiments, a forward bias voltage drop of the first diode device is greater than a threshold voltage of the first transistor. In some embodiments, a forward bias voltage drop of the first diode device is less than a voltage difference between the first and second logic levels. In some embodiments, one or both of the first or second diode devices includes a plurality of diode-connected transistors coupled in series. In some embodiments, the pumping stage circuit includes a first driver coupled between the first control signal terminal and the first capacitive device and a second driver coupled between the second control signal terminal and the second capacitive device. In some embodiments, the output stage circuit includes a third control signal terminal configured to receive the first control signal, a third capacitive device coupled between the third control signal terminal and a second gate terminal of the second transistor, a fourth capacitive device coupled between the output node and a supply reference terminal configured to have a voltage level the same as the logic low level, a third diode device including a third anode coupled to the second gate terminal and a third cathode coupled to the fourth S/D terminal, and a fourth diode device including a fourth cathode coupled to the second gate terminal and a fourth anode coupled to the fourth S/D terminal.

In some embodiments, a charge pump circuit includes input and output nodes, a control circuit configured to output first and second control signals, a pumping stage circuit and an output stage circuit coupled in series between the input and output nodes, wherein each of the pumping stage and output stage circuits includes input and output terminals, first and second diode devices, a transistor including a first S/D terminal coupled to the input terminal, a second S/D terminal coupled to the output terminal, a cathode of the first diode device, and an anode of the second diode device, and a gate terminal coupled to an anode of the first diode device and a cathode of the second diode device, a first driver configured to output a first driving signal based on the first control signal, a first capacitive device coupled to the first driver and the gate terminal, and a second capacitive device coupled to the output terminal. The pumping stage circuit includes a second driver coupled to the second capacitive device and configured to output a second driving signal based on the second control signal, the control circuit is configured to generate the first control signal including a first transition from a first logic level to a second logic level at a first time and the second control signal including a second transition from the first logic level to the second logic level at a second time, and a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the first time to the second time to be less than 100 millivolts. In some embodiments, the control circuit is configured to generate the second control signal including a third transition from the second logic level to the first logic level at a third time and the first control signal including a fourth transition from the second logic level to the first logic level at a fourth time, and another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the third time to the fourth time to be less than 100 millivolts. In some embodiments, one or more of the first or second driver of the pumping stage circuit or the first driver of the output stage circuit includes an inverter, a buffer, or a level shifter. In some embodiments, the control circuit is configured to generate the first control signal and the first driver is configured to output the first driving signal each having a first voltage level corresponding to the first or second logic level being a logic high level, the control circuit is configured to generate the second control signal and the second driver is configured to output the second driving signal each having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level. In some embodiments, the control circuit is configured to generate each of the first and second control signals having a first voltage level corresponding to the first or second logic level being a logic high level, the first and second drivers are configured to output each of the respective first and second driving signals having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level. In some embodiments, a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device. In some embodiments, the control circuit includes a two-phase, non-overlapping clock generator configured to generate the first and second control signals. In some embodiments, the second capacitive device of the output stage circuit is coupled to a supply reference terminal configured to have a reference ground voltage level.

In some embodiments, a method of operating a charge pump circuit includes generating a first transition in a first control signal from a first predetermined voltage level to a second predetermined voltage level at a first time, generating a second transition in a second control signal from the first predetermined voltage level to the second predetermined voltage level at a second time, operating a pumping stage circuit of the charge pump circuit by causing a first voltage at a first end of a first capacitive device to transition from a first voltage level to a second voltage level responsive to the first transition in the first control signal, the first end of the first capacitive device being electrically coupled to a gate terminal of a first transistor, and causing a second voltage at a second end of a second capacitive device to transition from a third voltage level to a fourth voltage level responsive to the second transition in the second control signal, the second end of the second capacitive device being electrically coupled to a S/D terminal of the first transistor, wherein a first diode device includes a first anode coupled to the gate terminal of the first transistor and a first cathode connected to the S/D terminal of the transistor, and a second diode device includes a second cathode coupled to the gate terminal of the first transistor and a second anode connected to the S/D terminal of the transistor. The method includes operating a pumping stage circuit of the charge pump circuit by generating an output voltage based on an output of the pumping stage circuit, wherein a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts. In some embodiments, the method includes generating a third transition in the second control signal from the second predetermined voltage level to the first predetermined voltage level at a third time, and generating a fourth transition in the first control signal from the second predetermined voltage level to the first predetermined voltage level at a fourth time, wherein another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts. In some embodiments, causing the first voltage at the first end of the first capacitive device to transition from the first voltage level to the second voltage level includes outputting a first driving signal from a first inverter responsive to the first transition in the first control signal, and causing the second voltage at the second end of the second capacitive device to transition from the third voltage level to the fourth voltage level includes outputting a second driving signal from a second inverter responsive to the second transition in the second control signal. In some embodiments, generating each of the first transition in the first control signal and the second transition in the second control signal includes generating one of the first or second predetermined voltage levels corresponding to a logic high level, outputting each of the first and second driving signals includes outputting a third predetermined voltage level corresponding to the logic high level, and the one of the first or second predetermined voltage levels corresponding to the logic high level is greater than the third predetermined voltage level.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A charge pump circuit, comprising: input and output nodes; an output stage circuit coupled to the output node; a pumping stage circuit coupled between the input node and the output stage circuit; and a control circuit configured to output first and second control signals to respective first and second control signal terminals of the pumping stage circuit; wherein the pumping stage circuit comprises: a first input terminal; an output terminal; a first transistor comprising a first source/drain (S/D) terminal coupled to the first input terminal, a second S/D terminal coupled to the output terminal, and a first gate terminal; a first capacitive device coupled between the first control signal terminal and the first gate terminal; a second capacitive device coupled between the second control signal terminal and the second S/D terminal; a first diode device comprising a first anode coupled to the first gate terminal and a first cathode coupled to the second S/D terminal; and a second diode device comprising a second cathode coupled to the first gate terminal and a second anode coupled to the second S/D terminal, the output stage circuit comprises: a second input terminal; and a second transistor comprising a third S/D terminal coupled to the second input terminal and a fourth S/D terminal coupled to the output node, the control circuit is configured to generate the first control signal comprising a first transition from a first logic level to a second logic level at a first time and the second control signal comprising a second transition from the first logic level to the second logic level at a second time, and a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the second S/D terminal of the first transistor from the first time to the second time to be less than 100 millivolts.
 2. The charge pump circuit of claim 1, wherein the control circuit is configured to generate the second control signal comprising a third transition from the second logic level to the first logic level at a third time and the first control signal comprising a fourth transition from the second logic level to the first logic level at a fourth time, and another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the second S/D terminal of the first transistor from the third time to the fourth time to be less than 100 millivolts.
 3. The charge pump circuit of claim 1, wherein a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device.
 4. The charge pump circuit of claim 1, wherein a forward bias voltage drop of the first diode device is greater than a threshold voltage of the first transistor.
 5. The charge pump circuit of claim 1, wherein a forward bias voltage drop of the first diode device is less than a voltage difference between the first and second logic levels.
 6. The charge pump circuit of claim 1, wherein one or both of the first or second diode devices comprises a plurality of diode-connected transistors coupled in series.
 7. The charge pump circuit of claim 1, wherein the pumping stage circuit further comprises: a first driver coupled between the first control signal terminal and the first capacitive device; and a second driver coupled between the second control signal terminal and the second capacitive device.
 8. The charge pump circuit of claim 1, wherein the output stage circuit further comprises: a third control signal terminal configured to receive the first control signal; a third capacitive device coupled between the third control signal terminal and a second gate terminal of the second transistor; a fourth capacitive device coupled between the output node and a supply reference terminal configured to have a voltage level the same as the logic low level; a third diode device comprising a third anode coupled to the second gate terminal and a third cathode coupled to the fourth S/D terminal; and a fourth diode device comprising a fourth cathode coupled to the second gate terminal and a fourth anode coupled to the fourth S/D terminal.
 9. A charge pump circuit, comprising: input and output nodes; a control circuit configured to output first and second control signals; a pumping stage circuit and an output stage circuit coupled in series between the input and output nodes, wherein each of the pumping stage and output stage circuits comprises: input and output terminals; first and second diode devices; a transistor comprising: a first source/drain (S/D) terminal coupled to the input terminal; a second S/D terminal coupled to the output terminal, a cathode of the first diode device, and an anode of the second diode device; and a gate terminal coupled to an anode of the first diode device and a cathode of the second diode device; a first driver configured to output a first driving signal based on the first control signal; a first capacitive device coupled to the first driver and the gate terminal; and a second capacitive device coupled to the output terminal, wherein the pumping stage circuit further comprises a second driver coupled to the second capacitive device and configured to output a second driving signal based on the second control signal, the control circuit is configured to generate the first control signal comprising a first transition from a first logic level to a second logic level at a first time and the second control signal comprising a second transition from the first logic level to the second logic level at a second time, and a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the first time to the second time to be less than 100 millivolts.
 10. The charge pump circuit of claim 9, wherein the control circuit is configured to generate the second control signal comprising a third transition from the second logic level to the first logic level at a third time and the first control signal comprising a fourth transition from the second logic level to the first logic level at a fourth time, and another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the third time to the fourth time to be less than 100 millivolts.
 11. The charge pump circuit of claim 9, wherein one or more of the first or second driver of the pumping stage circuit or the first driver of the output stage circuit comprises an inverter, a buffer, or a level shifter.
 12. The charge pump circuit of claim 9, wherein the control circuit is configured to generate the first control signal and the first driver is configured to output the first driving signal each having a first voltage level corresponding to the first or second logic level being a logic high level, the control circuit is configured to generate the second control signal and the second driver is configured to output the second driving signal each having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level.
 13. The charge pump circuit of claim 9, wherein the control circuit is configured to generate each of the first and second control signals having a first voltage level corresponding to the first or second logic level being a logic high level, the first and second drivers are configured to output each of the respective first and second driving signals having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level.
 14. The charge pump circuit of claim 9, wherein a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device.
 15. The charge pump circuit of claim 9, wherein the control circuit comprises a two-phase, non-overlapping clock generator configured to generate the first and second control signals.
 16. The charge pump circuit of claim 9, wherein the second capacitive device of the output stage circuit is coupled to a supply reference terminal configured to have a reference ground voltage level.
 17. A method of operating a charge pump circuit, the method comprising: generating a first transition in a first control signal from a first predetermined voltage level to a second predetermined voltage level at a first time; generating a second transition in a second control signal from the first predetermined voltage level to the second predetermined voltage level at a second time; operating a pumping stage circuit of the charge pump circuit by: causing a first voltage at a first end of a first capacitive device to transition from a first voltage level to a second voltage level responsive to the first transition in the first control signal, the first end of the first capacitive device being electrically coupled to a gate terminal of a first transistor; and causing a second voltage at a second end of a second capacitive device to transition from a third voltage level to a fourth voltage level responsive to the second transition in the second control signal, the second end of the second capacitive device being electrically coupled to a source/drain (S/D) terminal of the first transistor, wherein a first diode device comprises a first anode coupled to the gate terminal of the first transistor and a first cathode connected to the S/D terminal of the transistor, and a second diode device comprises a second cathode coupled to the gate terminal of the first transistor and a second anode connected to the S/D terminal of the transistor; and operating a pumping stage circuit of the charge pump circuit by generating an output voltage based on an output of the pumping stage circuit, wherein a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts.
 18. The method of claim 17, further comprising: generating a third transition in the second control signal from the second predetermined voltage level to the first predetermined voltage level at a third time; and generating a fourth transition in the first control signal from the second predetermined voltage level to the first predetermined voltage level at a fourth time, wherein another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts.
 19. The method of claim 17, wherein the causing the first voltage at the first end of the first capacitive device to transition from the first voltage level to the second voltage level comprises outputting a first driving signal from a first inverter responsive to the first transition in the first control signal, and the causing the second voltage at the second end of the second capacitive device to transition from the third voltage level to the fourth voltage level comprises outputting a second driving signal from a second inverter responsive to the second transition in the second control signal.
 20. The method of claim 19, wherein the generating each of the first transition in the first control signal and the second transition in the second control signal comprises generating one of the first or second predetermined voltage levels corresponding to a logic high level, the outputting each of the first and second driving signals comprises outputting a third predetermined voltage level corresponding to the logic high level, and the one of the first or second predetermined voltage levels corresponding to the logic high level is greater than the third predetermined voltage level. 